1. Field of the Invention
The invention relates to a method of manufacturing ICs, and more particularly to a method of forming a capacitor for dynamic random access memory (DRAM).
2. Description of the Related Art
In line with continuously enhanced functions in microprocessors for handling much more operations during running programs, high-quality and performance of capacitors in memory cells are urgently required. In general each memory cell included in a high-integration of DRAM consists of a transfer field effect transistor T and a storage capacitor C as shown in FIG. 1. The capacitor C included in an array of capacitors formed on the surface of a semiconductor substrate is used to store one-bit data in a form of binary by charging/discharging. Typically it is defined that the capacitor C stores one-bit data with a logic level 0 when uncharged while stores one-bit data with a logic level 1 when charged. Furthermore, a dielectric 100 fills the space between an upper electrode 102 and a lower electrode 100 for providing a dielectric constant required by the capacitor C. As shown in FIG. 1, the drain of the transfer field effect transistor T is electrically coupled to a bit line BL while the source thereof is electrically coupled to one end of the capacitor C. Moreover the gate of the transfer field effect transistor T is electrically coupled to a word line WL which is used to determine whether the transfer field effect transistor T is turned on to electrically connect the bit line and the capacitor C. As can be obviously seen from the above, the capacitor C is indirectly connected to a bit line BL for data access by charging/discharging in coordination with the transfer field effect transistor T.
In a traditional DRAM with a storage capacity of at least 1M bits, 2-dimensional capacitors, called planar type capacitors, are mainly used to store data. However, the planar type capacitors are not suitable for a high-integration of DRAM because take up much more spaces for data storage. Therefore, a high-integration of DRAM with, for example, a storage capacity of 4M bits. needs 3-dimensional capacitors such as stacked type capacitors or trench type capacitors, to complete the performances thereof.
Compared to the planar type capacitors the stacked type capacitors or the trench type capacitors can obtains a great amount of capacitance eve though the DRAM is further reduced in size. However, the simple 3-dimensional capacitor structure is no longer adapted when a much higher-integration of DRAM is introduced.
To resolve this problem a fin type capacitor having electrodes and a corresponding dielectric layer stacked on each other and extended towards the horizontal direction to increase surface areas, resulting in the increase of the capacitance thereof. has been developed. References for related technologies can be made to "3-dimensional stacked capacitor cell for 16M and 64M DRAMs", International Electron Devices Meeting, pp592-595 written by Ema et. al. and U.S. Pat. Nos. 5,071,783, 5,126,810 and 5,206,787.
Additionally to resolve this problem, a cylindrical type capacitor where electrodes and a corresponding dielectric layer are extended to form a vertical structure has been developed. Since the surface areas of the cylindrical type capacitor is increased, the capacitance thereof is increased. References for related technologies can be made to "Novel Stacked capacitor Cell for 64 Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp69-70 written by Wakamiya et. al. and U.S. Pat. No. 5,077,688.
Duo to the requirement of continuously increasing integration the memory cells of DRAM need to be further shrunk. It is well known by those skilled in the art that the more the memory cells shrink, the less the capacitance thereof will be. This causes the probability of soft error created by the incidence of .alpha. ray to increase. Therefore, a structure and a method of forming a capacitor having a desired capacitance. even though the capacitor is further reduced in size, is urgently required.